Enum std::sync::atomic::Ordering

#[non_exhaustive]
pub enum Ordering {
    Relaxed,
    Release,
    Acquire,
    AcqRel,
    SeqCst,
}

Atomic memory orderings

Memory orderings specify the way atomic operations synchronize memory. In its weakest Relaxed, only the memory directly touched by the operation is synchronized. On the other hand, a store-load pair of SeqCst operations synchronize other memory while additionally preserving a total order of such operations across all threads.

Rust's memory orderings are the same as LLVM's.

For more information see the nomicon.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

Relaxed

No ordering constraints, only atomic operations.

Corresponds to LLVM's Monotonic ordering.

Release

When coupled with a store, all previous operations become ordered before any load of this value with Acquire (or stronger) ordering. In particular, all previous writes become visible to all threads that perform an Acquire (or stronger) load of this value.

Notice that using this ordering for an operation that combines loads and stores leads to a Relaxed load operation!

This ordering is only applicable for operations that can perform a store.

Corresponds to LLVM's Release ordering.

Acquire

When coupled with a load, if the loaded value was written by a store operation with Release (or stronger) ordering, then all subsequent operations become ordered after that store. In particular, all subsequent loads will see data written before the store.

Notice that using this ordering for an operation that combines loads and stores leads to a Relaxed store operation!

This ordering is only applicable for operations that can perform a load.

Corresponds to LLVM's Acquire ordering.

AcqRel

Has the effects of both Acquire and Release together: For loads it uses Acquire ordering. For stores it uses the Release ordering.

Notice that in the case of compare_and_swap, it is possible that the operation ends up not performing any store and hence it has just Acquire ordering. However, AcqRel will never perform Relaxed accesses.

This ordering is only applicable for operations that combine both loads and stores.

Corresponds to LLVM's AcquireRelease ordering.

SeqCst

Like Acquire/Release/AcqRel (for load, store, and load-with-store operations, respectively) with the additional guarantee that all threads see all sequentially consistent operations in the same order.

Corresponds to LLVM's SequentiallyConsistent ordering.

Trait Implementations

impl Debug for Ordering

fn fmt(&self, f: &mut Formatter) -> Result<(), Error>

Formats the value using the given formatter.

impl Hash for Ordering

fn hash<__H>(&self, state: &mut __H) where
    __H: Hasher, 

Feeds this value into the given [Hasher].

fn hash_slice<H>(data: &[Self], state: &mut H) where
    H: Hasher, 

Feeds a slice of this type into the given [Hasher].

impl Eq for Ordering

impl Clone for Ordering

fn clone(&self) -> Ordering

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq<Ordering> for Ordering

fn eq(&self, other: &Ordering) -> bool

This method tests for self and other values to be equal, and is used by ==.

#[must_use] fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl Copy for Ordering