[−][src]Function core::arch::mips64::__msa_srlri_d

pub unsafe fn __msa_srlri_d(a: v2i64, imm6: i32) -> v2i64

🔬 This is a nightly-only experimental API. (stdsimd #48556)

This is supported on MIPS-64 and target feature msa only.

Immediate Shift Right Logical Rounded

The elements in vector a (two signed 64-bit integer numbers) are shifted right logical by imm6 bits.The most significant discarded bit is added to the shifted value (for rounding) and the result is written to vector (two signed 64-bit integer numbers).