[−][src]Function core::arch::mips64::__msa_ilvr_d
pub unsafe fn __msa_ilvr_d(a: v2i64, b: v2i64) -> v2i64
This is supported on MIPS-64 and target feature
msa only.Vector Interleave Right
The right half elements in vectors a (two signed 64-bit integer numbers)
and vector b (two signed 64-bit integer numbers) are copied to the result
(two signed 64-bit integer numbers)
alternating one element from a with one element from b.