[−][src]Function core::arch::mips64::__msa_fsaf_d

pub unsafe fn __msa_fsaf_d(a: v2f64, b: v2f64) -> v2i64

🔬 This is a nightly-only experimental API. (stdsimd #48556)

This is supported on MIPS-64 and target feature msa only.

Vector Floating-Point Signaling Compare Always False

Set all bits to 0 in vector (two signed 64-bit integer numbers) elements. Signaling and quiet NaN elements in vector a (two 64-bit floating point numbers) or b (two 64-bit floating point numbers) signal Invalid Operation exception. In case of a floating-point exception, the default result has all bits set to 0.