[−][src]Function core::arch::mips64::__msa_fexupl_d

pub unsafe fn __msa_fexupl_d(a: v4f32) -> v2f64

🔬 This is a nightly-only experimental API. (stdsimd #48556)

This is supported on MIPS-64 and target feature msa only.

Vector Floating-Point Up-Convert Interchange Format Left

The left half floating-point elements in vector a (four 32-bit floating point numbers) are up-converted to a larger interchange format, i.e. from 16-bit to 32-bit, or from 32-bit to 64-bit. The result is written to vector (two 64-bit floating point numbers).