Function core::arch::mips64::__msa_fexp2_w

pub unsafe fn __msa_fexp2_w(a: v4f32, b: v4i32) -> v4f32

🔬 This is a nightly-only experimental API. (stdsimd #48556)

This is supported on MIPS-64 and target feature msa only.

Vector Floating-Point Down-Convert Interchange Format

The floating-point elements in vector a (four 32-bit floating point numbers) are scaled, i.e. multiplied, by 2 to the power of integer elements in vector b (four signed 32-bit integer numbers). The result is written to vector (four 32-bit floating point numbers).