Function core::arch::mips::__msa_fceq_d

pub unsafe fn __msa_fceq_d(a: v2f64, b: v2f64) -> v2i64

🔬 This is a nightly-only experimental API. (stdsimd #48556)

This is supported on MIPS and target feature msa only.

Vector Floating-Point Quiet Compare Equal

Set all bits to 1 in vector (two signed 64-bit integer numbers) elements if the corresponding in a (two 64-bit floating point numbers) and b (two 64-bit floating point numbers) elements are ordered and equal, otherwise set all bits to 0.