[−][src]Function core::arch::mips::__msa_aver_s_d
pub unsafe fn __msa_aver_s_d(a: v2i64, b: v2i64) -> v2i64
This is supported on MIPS and target feature
msa only.Vector Signed Average Rounded
The elements in vector a (two signed 64-bit integer numbers)
are added to the elements in vector b (two signed 64-bit integer numbers).
The addition of the elements plus 1 (for rounding) is done signed with full precision,
i.e. the result has one extra bit.
Signed division by 2 (or arithmetic shift right by one bit) is performed before
writing the result to vector (two signed 64-bit integer numbers).